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general description the max1864/max1865 power-supply controllers are designed to address cost-conscious applications such as cable modem consumer premise equipment (cpe), xdsl cpe, and set-top boxes. operating off a low-cost, unregulated dc supply (such as a wall adapter output), the max1864 generates three positive outputs, and the max1865 generates four positive outputs and one neg- ative output to provide a cost-effective system power supply. the max1864 includes a current-mode synchronous step-down controller and two positive regulator gain blocks. the max1865 has one additional positive gain block and one negative regulator gain block. the main synchronous step-down controller generates a high-current output that is preset to 3.3v or adjustable from 1.236v to 0.8 ? v in with an external resistive- divider. the 100khz/200khz operating frequency allows the use of low-cost aluminum-electrolytic capaci- tors and low-cost power magnetics. additionally, the max1864/max1865 step-down controllers sense the voltage across the low-side mosfet? on-resistance to efficiently provide the current-limit signal, eliminating the need for costly current-sense resistors. the max1864/max1865 generate additional supply rails at low cost. the positive regulator gain blocks use an external pnp pass transistor to generate low-voltage rails directly from the main step-down converter (such as 2.5v or 1.8v from the main 3.3v output) or higher voltages using coupled windings from the step-down converter (such as 5v, 12v, or 15v). the max1865? negative gain block uses an external npn pass transis- tor in conjunction with a coupled winding to generate -5v, -12v, or -15v. all output voltages are externally adjustable, providing maximum flexibility. additionally, the max1864/ max1865 feature soft-start for the step-down converter and all the positive linear regulators, and have a power- good output that monitors all of the output voltages. applications xdsl, cable, and isdn modems set-top boxes wireless local loop features 4.5v to 28v input voltage range master dc-dc step-down converter preset 3.3v or adjustable (1.236v to 0.8 ? v in ) output voltage fixed-frequency (100khz/200khz) pwm controller no current-sense resistor adjustable current limit 95% efficient two (max1864)/four (max1865) analog gain blocks positive analog blocks drive low-cost pnp pass transistors to build positive linear regulators negative analog block (max1865) drives a low-cost npn pass transistor to build a negative linear regulator power-good indicator soft-start ramp for all positive regulators max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pok in vl bst dh lx dl gnd ilim top view max1864 16 qsop comp out fb2 fb b2 b3 fb3 pin configurations ordering information 19-2030; rev 0; 4/01 part temp. range pin- package f osc (khz) max1864 teee -40 c to +85 c 16 qsop 200 max1864ueee -40 c to +85 c 16 qsop 100 max1865 teep -40 c to +85 c 20 qsop 200 max1865ueep -40 c to +85 c 20 qsop 100 pin configurations continued at end of data sheet. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = 12v, ilim = fb = gnd, v bst - v lx = 5v, t a = 0? to +85? . typical values are at t a = +25 c, unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, b2, b3, b4 to gnd............................................-0.3v to +30v b5 to out...............................................................-20v to +0.3v vl, pok, fb, fb2, fb3, fb4, fb5 to gnd ...............-0.3v to +6v lx to bst..................................................................-6v to +0.3v bst to gnd ............................................................-0.3v to +36v dh to lx ....................................................-0.3v to (v bst + 0.3v) dl, out, comp, ilim to gnd......................-0.3v to (v l + 0.3v) vl output current ...............................................................50ma vl short circuit to gnd................................................... 100ms continuous power dissipation (t a = +70 c) 16-pin qsop (derate 8.3mw/ c above +70 c)...........666mw 20-pin qsop (derate 9.1mw/ c above +70 c)...........727mw operating temperature range ...........................-40 c to +85 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter symbol conditions min typ max units general operating input voltage range (note 1) v in 4.5 28 v max1864 1.0 2 quiescent supply current i in v fb = 0, v out = 4v, v fb2 = v fb3 = v fb4 = 1.5v, v fb5 = -0.1v max1865 1.4 3 ma vl regulator output voltage vl 6v < v in < 28v, 0.1ma < i load < 20ma 4.75 5.00 5.25 v power-supply rejection psrr v in = 6v to 28v 3 % undervoltage lockout trip level v uvlo vl rising, 3% hysteresis (typ) 3.2 3.5 3.8 v minimum bypass capacitance c byp ( min ) 10m ? < esr < 500m ? 1f dc-dc controller output voltage (preset mode) v out fb = gnd 3.272 3.314 3.355 v typical output voltage range (adjustable mode) (note 2) v out 1.236 0.8 x v in v fb set voltage (adjustable mode) v set fb = comp 1.221 1.236 1.252 v fb dual mode threshold 50 100 150 mv fb input leakage current i fb v fb = 1.5v 0.01 100 na fb to comp transconductance g m fb = comp, i comp = 5a 70 100 140 s current-sense amplifier voltage gain a lim v in - v lx = 250mv 4.46 4.9 5.44 v/v current-limit threshold (internal mode) v valley v ilim = 5.0v 190 250 310 mv current-limit threshold (external mode) v valley v ilim = 2.5v 440 530 620 mv dual mode is a trademark of maxim integrated products, inc.
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units max186_t 160 200 240 switching frequency f osc max186_u 80 100 120 khz maximum duty cycle d max 77 82 90 % soft-start period t soft 1024 1/f osc soft-start steps v ref /64 v dh output low voltage i sink = 10ma, measured from dh to lx 0.1 v dh output high voltage i source = 10ma, measured from bst to dh 0.1 v dl output low voltage i sink = 10ma, measured from dl to gnd 0.1 v dl output high voltage i source = 10ma, measured from dl to gnd v l - 0.1 v dh, dl on-resistance 310 ? output drive current sourcing or sinking, v dh or v dl = vl/2 0.5 a lx, bst leakage current v bst = v lx = v in = 28v, v fb = 1.5v 0.03 20 a positive analog gain blocks fb2, fb3, fb4 regulation voltage v b2 = v b3 = v b4 = 5v, i b2 = i b3 = i b4 = 1ma (sink) 1.226 1.240 1.257 v fb2, fb3, fb4 to b_ transconductance ? v fb _ v b2 = v b3 = v b4 = 5v, i b2 = i b3 = i b4 = 0.5ma to 5ma (sink) -1 -1.75 % feedback input leakage current i fb _v fb2 = v fb3 = v fb4 = 1.5v 0.01 100 na v b2 = v b3 = v b4 = 2.5v 10 23 driver sink current i b _ v fb2 = v fb3 = v fb4 = 1.188v v b2 = v b3 = v b4 = 4.0v 26 ma negative analog gain block fb5 regulation voltage v b5 = v out - 2v, v out = 3.5v, i b5 = 1ma (source) -20 -5 +10 mv fb5 to b5 transconductance ? v fb5 v b5 = 0, i b5 = 0.5ma to 5ma (source) -13 -20 mv feedback input leakage current i fb5 v fb5 = -100mv 0.01 100 na driver source current i b5 v fb5 = 200mv, v b5 = v out - 2.0v, v out = 3.5v 10 25 ma power good (pok) out trip level (preset mode) fb = gnd, falling edge, 1% hysteresis (typ) 2.88 3 3.12 v fb trip level (adjustable mode) falling edge, 1% hysteresis (typ) 1.070 1.114 1.159 v fb2, fb3, fb4 trip level falling edge, 1% hysteresis (typ) 1.070 1.114 1.159 v fb5 trip level rising edge, 35mv hysteresis (typ) 368 500 632 mv pok output low level i sink = 1ma 0.4 v pok output high leakage v pok = 5v 1 a thermal protection (note 3) thermal shutdown rising temperature 160 c thermal shutdown hysteresis 15 c electrical characteristics (continued) (v in = 12v, ilim = fb = gnd, v bst - v lx = 5v, t a = 0 c to +85 c . typical values are at t a = +25 c, unless otherwise noted.)
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 4 _______________________________________________________________________________________ parameter symbol conditions min max units general operating input voltage range (note 1) v in 4.5 28 v max1864 2 quiescent supply current i in v fb = 0, v out = 4v, v fb2 = v fb3 = v fb4 = 1.5v, v fb5 = -0.1v max1865 3 ma vl regulator output voltage vl 6v < v in < 28v, 0.1ma < i load <20ma 4.75 5.25 v power-supply rejection psrr v in = 6v to 28v 3 % undervoltage lockout trip level v uvlo vl rising, 3% hysteresis (typ) 3 4 v dc-dc controller output voltage (preset mode) v out fb = gnd 3.247 3.380 v feedback set voltage (adjustable mode) v set fb = comp 1.211 1.261 v current-sense amplifier voltage gain a lim v in - v lx = 250mv 4.12 5.68 v/v current-limit threshold (internal mode) v valley v ilim = 5v 150 350 mv current-limit threshold (external mode) v valley v ilim = 2.5v 400 660 mv max186_t 160 240 switching frequency f osc max186_u 80 120 khz maximum duty cycle d max 74 90 % positive analog gain blocks fb2, fb3, fb4 regulation voltage v b2 = v b3 = v b4 = 5v, i b2 = i b3 = i b4 = 1ma (sink) 1.215 1.265 v fb2, fb3, fb4 to b_ transconductance ? v fb _ v b2 = v b3 = v b4 = 5v, i b2 = i b3 = i b4 = 0.5ma to 5ma (sink) -2.25 % negative analog gain block fb5 regulation voltage v b5 = v out - 2v, v out = 3.5v, i b5 = 1ma (source) -25 +10 mv fb5 to b5 transconductance ? v fb5 v b5 = 0, i b5 = 0.5ma to 5ma (source) -30 mv electrical characteristics (v in = 12v, ilim = fb = gnd, v bst - v lx = 5v, t a = -40 c to +85 c , unless otherwise noted.) (note 4)
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies _______________________________________________________________________________________ 5 note 1: connect vl to in for operation with v in < 5v. note 2: see output voltage selection section. note 3: the internal 5v linear regulator (vl) powers the thermal shutdown block. shorting vl to gnd disables thermal shutdown. note 4: specifications to -40 c are guaranteed by design, not production tested. electrical characteristics (continued) (v in = 12v, ilim = fb = gnd, v bst - v lx = 5v, t a = -40 c to +85 c , unless otherwise noted.) (note 4) parameter symbol conditions min max units power good (pok) out trip level (preset mode) fb = gnd, falling edge, 1% hysteresis (typ) 2.85 3.15 v fb trip level (adjustable mode) falling edge, 1% hysteresis (typ) 1.058 1.17 v fb2, fb3, fb4 trip level falling edge, 1% hysteresis (typ) 1.058 1.17 v fb5 trip level rising edge, 35mv hysteresis (typ) 325 675 mv 50 0.01 10 1 0.1 efficiency vs. load current (preset mode) 100 70 60 90 80 max1864/65 toc01 load current (a) efficiency (%) v in = 6.5v v in = 8v v in = 12v v in = 18v v in = 24v v out = 3.3v 3.27 3.29 3.28 3.31 3.30 3.32 3.33 0 1.0 1.5 0.5 2.0 2.5 3.0 output voltage vs. load current (preset mode) max1864/65 toc02 load current (a) output voltage (v) 50 0.01 10 1 0.1 efficiency vs. load current (adjustable mode) 100 70 60 90 80 max1864/65 toc03 load current (a) efficiency (%) v in = 6.5v v in = 8v v in = 12v v in = 18v v in = 24v v out = 5.0v typical operating characteristics (circuit of figure 1, v in = 12v, v out = 3.3v, t a = +25 c, unless otherwise noted.)
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 6 _______________________________________________________________________________________ 2 s/div switching waveforms (step-down converter) 3.35v 1.5a c a max1864/65 toc07 1a 0 3.30v a. v out = 3.3v (preset), i out = 1a, 50mv/div b. inductor current, 500ma/div c. v lx , 10v/div v in = 12v 10v 0.5a b 1ms/div soft-start 5v 4v b a max1864/65 toc08 2v 0 0 a. v l , 5v/div b. v out = 3.3v (preset), 2v/div c. inductor current, 1a/div v in = 0 to 12v 0 1a c 0 5 10 15 20 25 30 35 40 0246810 positive linear regulator base- drive current vs. base-drive voltag e max1864/65 toc09 base voltage (v) base-drive sink current (ma) v fb_ = 1.0v v fb_ = 0.96v ref b2, b3 and b4 (max1865) only typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v out = 3.3v, t a = +25 c, unless otherwise noted.) 4.95 4.97 4.99 5.01 5.03 5.05 01.0 0.5 1.5 2.0 2.5 3.0 ouput voltage vs. load current (adjustable mode) max1864/65 toc04 load current (ma) output voltage (v) 4.95 4.97 4.99 5.01 5.03 5.05 010 5 15202530 internal 5v linear regulator vs. load current max1864/65 toc05 load current (ma) vl (v) 1ms/div load transient (step-down converter) 3.5v 3.1v b a max1864/65 toc06 1a 0 3.3v a. v out = 3.3v (preset), 200mv/div b. i out = 10ma to 1a, 500ma/div v in = 12v
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies _______________________________________________________________________________________ 7 typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v out = 3.3v, t a = +25 c, unless otherwise noted.) 2.50 0.01 1 0.1 100 positive linear regulator output voltage vs. load current (q ldo = 2n3905) 2.42 2.44 2.46 2.48 max18664/65 toc10 load current (ma) output voltage (v) 10 1000 v sup(pos) = 5.0v v sup(pos) = 3.3v 2.42 2.44 2.46 2.48 2.50 24 3 5678 positive linear regulator output voltage vs. supply voltage (q ldo = 2n3905) max1864/65 toc11 supply voltage (v) output voltage (v) i out2 = 1ma i out2 = 100ma 80 70 60 50 40 30 20 10 0 0.1 10 100 1 1000 positive linear regulator power-supply rejection ratio (q ldo = 2n3905) max1864/65 toc12 frequency (khz) psrr (db) i out2 = 50ma positive linear regulator load transient (q ldo = 2w3905) max1864/65 toc13 100ma 2.457v 2.467v a. i outz = 1ma to 100ma, 50ma/div b. v outz = 2.5v, 5mv/div c ldo(pos) = 10 f ceramic, v sup(pos) = 3.3v circuit of figure 1 0 b a 10 s/div 2.50 0.01 0.1 1000 100 positive linear regualtor output voltage vs. load current (q ldo = tip30) 2.42 2.44 2.46 2.48 max1864/65 toc14 load current (ma) output voltage (v) 110 v sup(pos) = 5.0v v sup(pos) = 3.3v 2.42 2.44 2.46 2.48 2.50 24681012 positive linear regulator output voltage vs. supply voltage (q ldo = tip30) max1864/65 toc15 supply voltage (v) output voltage (v) i out2 = 1ma i out2 = 100ma
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 8 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, v in = 12v, v out = 3.3v, t a = +25 c, unless otherwise noted.) -12.00 -12.06 -12.12 -12.18 -12.24 0.01 1 10 100 0.1 1000 negative linear regulator output voltage vs. load current (q ldo = tip29) max1864/65 toc19 load current (ma) output voltage (v) v sup(neg) = -15v v out3 = 5v -12.24 -12.18 -12.12 -12.06 -12.00 -20 -18 -16 -14 -12 -10 negative linear regulator output voltage vs. supply voltage (q ldo = tip29) max1864/65 toc20 supply voltage (v) output voltage (v) i ldo(neg) = 100ma i ldo(neg) = 1ma 80 70 60 50 40 30 20 10 0 0.1 10 100 11000 positive linear regulator power-supply rejection ratio (q ldo = tip30) max1864/65 toc16 frequency (khz) psrr (db) i out2 = 150ma positive linear regulator load transient (q ldo = tip30) max1864/65 toc17 250ma 2.453v 2.473v a. i out2 = 10ma to 250ma, 200ma/div b. v out2 = 2.5v, 10mv/div c ldo(pos) = 10 f ceramic, v sup(pos) = 3.3v circuit of figure 1 0 b a 10 s 0 10 5 25 20 15 40 35 30 45 04 26810 negative linear regulator base- drive current vs. base-drive voltage max1864/65 toc18 v out - v b5 (v) base-drive source current (ma) v fb5 = 250mv v fb5 = 50mv v out = 5.0v v out = 3.3v b5 (max1865) only
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies _______________________________________________________________________________________ 9 pin description pin max1864 max1865 name function 1 1 pok open-drain power-good output. pok is low when the output voltage is more than 10% below the regulation point. pok is high impedance when the output is in regulation. connect a resistor between pok and vl for logic-level voltages. 2 2 comp compensation pin. connect a series rc to gnd to compensate the control loop. typical values are 47k ? and 8.2nf. 3 3 out regulated output voltage high-impedance sense input. internally connected to a resistive-divider and negative gain block (max1865). 44fb dual-mode switching-regulator feedback input. connect to gnd for the preset 3.3v output. connect to a resistive-divider from output to fb to gnd to adjust the output voltage between 1.236v and 0.8 ? v in . the feedback set point is 1.236v. 55b2 open-drain output pnp transistor driver (regulator #2). internally connected to the drain of a dmos. b2 connects to the base of an external pnp pass transistor to form a positive linear regulator. 6 6 fb2 analog gain-block feedback input (regulator #2). connect to a resistive-divider between the positive linear regulator s output and gnd to adjust the output voltage. the feedback set point is 1.24v. 77b3 open-drain output pnp transistor driver (regulator #3). internally connected to the drain of a dmos. b3 connects to the base of an external pnp pass transistor to form a positive linear regulator. 8 8 fb3 analog gain-block feedback input (regulator #3). connect to a resistive-divider between the positive linear regulator s output and gnd to adjust the output voltage. the feedback set point is 1.24v. 9b4 open-drain output pnp transistor driver (regulator #4). internally connected to the drain of a dmos. b4 connects to the base of an external pnp pass transistor to form a positive linear regulator. 10 fb4 analog gain-block feedback input (regulator #4). connect to a resistive-divider between the positive linear regulator s output and gnd to adjust the output voltage. the feedback set point is 1.24v. 11 b5 open-drain output npn transistor driver (regulator #5). internally connected to the drain of a p-channel mosfet. b5 connects to the base of an external npn pass transistor to form a negative linear regulator. 12 fb5 analog gain-block feedback input (regulator #5). connect to a resistive-divider between the negative linear regulator s output and a positive reference voltage, typically one of the positive linear regulator outputs, to adjust the output voltage. the feedback set point is at gnd.
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 10 ______________________________________________________________________________________ detailed description the max1864/max1865 power-supply controllers pro- vide system power for cable and xdsl modems. the main step-down dc-dc controller operates in a cur- rent-mode pulse-width-modulation (pwm) control scheme to ease compensation requirements and pro- vide excellent load- and line-transient response. the max1864 includes two analog gain blocks to regu- late two additional positive auxiliary output voltages, and the max1865 includes four analog gain blocks to regulate three additional positive and one negative aux- iliary output voltages. the positive regulator gain blocks can be used to generate low-voltage rails directly from the main step-down converter or higher voltages using coupled windings from the step-down converter. the negative gain block can be used in conjunction with a coupled winding to generate -5v, -12v, or -15v. dc-dc controller the max1864/max1865 step-down converters use a pulse-width-modulated (pwm) current-mode control scheme (figure 2). an internal transconductance amplifier establishes an integrated error voltage at the comp pin. the heart of the current-mode pwm con- troller is an open-loop comparator that compares the integrated voltage-feedback signal against the ampli- fied current-sense signal plus the slope compensation ramp. at each rising edge of the internal clock, the high-side mosfet turns-on until the pwm comparator trips or the maximum duty cycle is reached. during this on-time, current ramps up through the inductor, sourc- ing current to the output and storing energy in a mag- netic field. the current-mode feedback system regulates the peak inductor current as a function of the output voltage error signal. since the average inductor current is nearly the same as the peak inductor current (assuming that the inductor value is relatively high to minimize ripple current), the circuit acts as a switch- mode transconductance amplifier. it pushes the output lc filter pole, normally found in a voltage-mode pwm, to a higher frequency. to preserve inner loop stability and eliminate inductor stair-casing, a slope-compensa- tion ramp is summed into the main pwm comparator. during the second-half of the cycle, the high-side mos- fet turns off and the low-side n-channel mosfet turns on. now the inductor releases the stored energy as its current ramps down, providing current to the output. therefore, the output capacitor stores charge when the inductor current exceeds the load current and dis- charges when the inductor current is lower, smoothing pin description (continued) pin max1864 max1865 name function 9 13 ilim dual-mode current-limit adjustment input. connect to vl for the default 250mv current-limit threshold. in adjustable mode, the current-limit threshold voltage is 1/5th the voltage present at ilim. connect to a resistive-divider between vl and gnd to adjust v ilim between 1v and 2.5v. the logic threshold for switchover to the 250mv default value is approximately vl - 1v. 10 14 gnd ground 11 15 dl low-side gate-driver output. dl swings between gnd and vl. 12 16 lx inductor connection. used for current sense between in and lx, and used for current limit between lx and gnd. 13 17 dh high-side gate-driver output. dh swings between lx and bst. 14 18 bst boost flying capacitor connection. connect bst to the external boost diode and capacitor as shown in the standard application circuit (figures 1 and 6). 15 19 vl internal 5v linear-regulator output. supplies the ic and powers the dl low-side gate driver and external boost diode and capacitor. bypass with a 1 f or greater ceramic capacitor to gnd. 16 20 in input supply voltage, 4.5v to 28v. bypass to gnd with a 1 f or greater ceramic capacitor close to the ic.
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 11 the voltage across the load. under overload conditions, when the inductor current exceeds the selected cur- rent-limit (see current limit ), the high-side mosfet is not turned on at the rising edge of the clock and the low-side mosfet remains on to let the inductor current ramp down. the max1864/max1865 operate in a forced-pwm mode, so even under light loads the controller main- tains a constant switching frequency to minimize cross- regulation errors in applications that use a transformer. the low-side gate-drive waveform is the complement of the high-side gate-drive waveform, which causes the inductor current to reverse under light loads. current-sense amplifier the max1864/max1865s current-sense circuit ampli- fies (a v = 5) the current-sense voltage generated by the high-side mosfet s on-resistance (r ds(on) ? i inductor ). this amplified current-sense signal and the internal slope compensation signal are summed together (v sum ) and fed into the pwm comparator s inverting input. the pwm comparator turns-off the high- side mosfet when v sum exceeds the integrated feed- back voltage (v comp) . place the high-side mosfet no further than 5mm from the controller, and connect in and lx to the mosfet using kelvin sense connections to guarantee current-sense accuracy and improve stability. bst c1 1 f d1 central cmpsh-3 c2 1 f n h n l c bst 0.1 f r pok 100k ? c comp c out 470 f c in 470 f dh lx t1 v out = 3.3v 1a input 9v to 18v dl out gnd in vl ilim pok comp max1864 fb 8.2nf r comp 47k ? r dh 10 ? 1 r dl 10 ? r be2 220 ? c3 10 f q1 r1 10k ? v out2 = 2.5v 300ma c4 10 f t1 r2 10k ? r be3 220 ? q2 c6 10 f r3 30k ? r4 10k ? c7 10 f v out3 = 5.0v 100ma c5 470 f d2 nihon ep05q03l b2 fb2 b3 fb3 c be3 4700pf c be2 2200pf nl, nh: international rectifier irf7303 q1: tip30 q2: 2n3905 figure 1. standard max1864 application circuit
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 12 ______________________________________________________________________________________ bias ok v ref 1.114v thermal shdn 3.5v in vl ldo 5v vl bst dh lx dl gnd 100k ? 400k ? ilim 0.9 ? vl pok enable 250mv a v = 5 500mv fb5* b5* *max1865 only out 0.9v ref fb1 0.9v ref b_ fb_ 100mv fb out comp fb1 soft- start v ref 1.236v clk slope comp a v = 5 enable max1864 max1865 figure 2. functional diagram
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 13 current-limit circuit the current-limit circuit employs a unique valley cur- rent-limiting algorithm that uses the low-side mosfet s on-resistance as a sensing element (figure 3). if the voltage across the low-side mosfet (r ds(on) ? i in- ductor ) exceeds the current-limit threshold at the beginning of a new oscillator cycle, the max1864/ max1865 will not turn on the high-side mosfet. the actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the low- side mosfet on-resistance, inductor value, input volt- age, and output voltage. the reward for this uncertainty is robust, loss-less overcurrent limiting. in adjustable mode, the current-limit threshold voltage is 1/5th the voltage seen at ilim (i valley = 0.2 ? v ilim ). adjust the current-limit threshold by connecting a resis- tive-divider from vl to ilim to gnd. the current-limit threshold can be set from 106mv to 530mv, which cor- responds to ilim input voltages of 500mv to 2.5v. this adjustable current limit accommodates mosfets with a wide range of on-resistance characteristics (see design procedure ). the current-limit threshold defaults to 250mv when ilim is connected to vl. the logic threshold for switchover to the 250mv default value is approximately vl - 1v. carefully observe the pc board layout guidelines to ensure that noise and dc errors don t corrupt the cur- rent-sense signals seen by lx and gnd. the ic must be mounted close to the low-side mosfet with short (less than 5mm), direct traces making a kelvin sense connection. synchronous rectifier driver (dl) synchronous rectification reduces conduction losses in the rectifier by replacing the normal schottky catch diode with a low-resistance mosfet switch. the max1864/max1865 also use the synchronous rectifier to ensure proper startup of the boost gate-driver circuit and to provide the current-limit signal. the dl low-side drive waveform is always the comple- ment of the dh high-side drive waveform (with con- trolled dead time to prevent cross-conduction or shoot-through ). a dead-time circuit monitors the dl output and prevents the high-side fet from turning on until dl is fully off. for the dead-time circuit to work properly, there must be a low-resistance, low-induc- tance path from the dl driver to the mosfet gate. otherwise, the sense circuitry in the max1864/ max1865 will interpret the mosfet gate as off when gate charge actually remains. use very short, wide traces (50mil to 100mil wide if the mosfet is 1 inch from the device). the dead time at the other edge (dh turning off) is determined by a fixed internal delay. high-side gate-drive supply (bst) gate-drive voltage for the high-side n-channel switch is generated by a flying-capacitor boost circuit (figure 1). the capacitor between bst and lx is alternately charged from the vl supply and placed parallel to the high-side mosfet s gate-source terminals. on startup, the synchronous rectifier (low-side mos- fet) forces lx to ground and charges the boost capacitor to 5v. on the second half-cycle, the switch- mode power supply turns on the high-side mosfet by closing an internal switch between bst and dh. this provides the necessary gate-to-source voltage to turn on the high-side switch, an action that boosts the 5v gate-drive signal above the battery voltage. internal 5v linear regulator (vl) all max1864/max1865 functions, except the current- sense amplifier, are internally powered from the on- chip, low-dropout 5v regulator. the maximum regulator input voltage (v in ) is 28v. bypass the regulator s output (vl) with at least a 1f ceramic capacitor to gnd. the v in -to-vl dropout voltage is typically 200mv, so when v in is less than 5.2v, vl is typically v in - 200mv. the internal linear regulator can source up to 20ma to supply the ic, power the low-side gate driver, charge the external boost capacitor, and supply small external loads. when driving particularly large fets, little or no regulator current may be available for external loads. for example, when switched at 200khz, a large fet with 40nc total gate charge requires 40nc x 200khz, or 8ma. inductor current i valley i load [ () ] time -i peak l v out v in f osc (v in - v out ) i peak = i valley + figure 3. ?alley?current-limit threshold point
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 14 ______________________________________________________________________________________ undervoltage lockout if vl drops below 3.5v, the max1864/max1865 assume that the supply voltage is too low to make valid decisions, so the undervoltage lockout (uvlo) circuitry inhibits switching, forces pok low, and forces the dl and dh gate drivers low. after vl rises above 3.5v, internal digital soft-start is initiated (see soft-start ). startup sequence externally, the max1864/max1865 starts switching when vl rises above the 3.5v undervoltage lockout threshold. however, the controller is not enabled unless all four of the following conditions are met: 1) vl exceeds the 3.5v undervoltage lockout threshold, 2) the internal reference exceeds 90% of its nominal value (v ref > 1.114v), 3) the internal bias circuitry powers up, and 4) the thermal limit is not exceeded. once the max1864/max1865 assert the internal enable signal, the step-down controller starts switching and enables soft-start. soft-start upon power-up, the max1864/max1865 begin a start- up sequence. first, the reference powers up. then, the main dc-dc step-down converter and positive linear regulators power up with soft-start enabled. once the regulators reach 90% of their nominal value and soft- start is complete, the active-high ready signal (pok) goes high (see power-good output ). soft-start gradually ramps up to the reference voltage in order to control the rate of rise of the output voltages and reduce input surge currents during startup. the soft-start period is 1024 clock cycles (1024/f osc ), and the internal soft-start dac ramps up the voltage in 64 steps. the output reaches regulation when soft-start is completed, regardless of output capacitance and load. power-good output the power-good output (pok) is an open-drain output. the mosfet turns on and pulls pok low when any out- put is less than 90% of its nominal regulation voltage or during soft-start. once all of the outputs exceed 90% of their nominal regulation voltages and soft-start is com- pleted, pok goes high impedance. to obtain a logic voltage output, connect a pullup resistor from pok to vl. a 100k ? resistor works well for most applications. if unused, leave pok grounded or unconnected. thermal-overload protection thermal-overload protection limits total power dissipa- tion in the max1864/max1865. when the junction tem- perature exceeds t j = +160 c, a thermal sensor shuts down the device, forcing dl and dh low, allowing the ic to cool. the thermal sensor turns the part on again after the junction temperature cools by 10 c, resulting in a pulsed output during continuous thermal-overload conditions. if the vl output is short circuited, thermal- overload protection is disabled. during a thermal event, the main step-down converter and the linear regulators are turned off, pok goes low, and soft-start is reset. design procedure dc-dc step-down converter output voltage selection the step-down controller s feedback input features dual-mode operation. connect the output to out and connect fb to gnd for the preset 3.3v output voltage. alternatively, the max1864/max1865 output voltage may be adjusted by connecting a voltage-divider from the output to fb to gnd (figure 4). select r2 in the 5k ? to 50k ? range. calculate r1 with the following equation: where v set = 1.236v, and v out may range from 1.236v to approximately 0.8 x v in (up to 20v). if v out > 5.5v, then connect out to gnd (max1864) or to one of the positive linear regulators (max1865) with an out- put voltage between 2v and 5v. inductor value three key inductor parameters must be specified: inductance value (l), peak current (i peak ), and dc resistance (r dc ). the following equation includes a constant lir, which is the ratio of inductor peak-to- peak ac current to dc load current. a higher lir value allows smaller inductance but results in higher losses and higher output ripple. a good compromise between size and losses is a 30% ripple-current to load-current ratio (lir = 0.3). the switching frequency, input volt- age, output voltage, selected lir determine the induc- tor value as follows: l vvv vi lir out in out in sw load max = () ? - () rr v v out set 12 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? -
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 15 where f sw is 200khz for max186_t and 100khz for max186_u. the exact inductor value is not critical and can be adjusted to make trade-offs among size, cost, and efficiency. lower inductor values minimize size and cost, but they also increase the output ripple and reduce the efficiency due to higher peak currents. on the other hand, higher inductor values increase effi- ciency, but at some point resistive losses due to extra turns of wire will exceed the benefit gained from lower ac current levels. find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. ferrite cores are often the best choice, though powdered iron is inexpensive and can work well at 200khz. the cho- sen inductor s saturation rating must exceed the peak inductor current: setting the current limit the minimum current-limit threshold must be high enough to support the maximum load current at the minimum tolerance level of the current-limit circuit. the valley of the inductor current occurs at i load(max) minus half of the ripple current: where r ds(on) is the on-resistance of the low-side mosfet (n l ). for the max1864/max1865, the mini- mum current-limit threshold is 190mv (for the typical 250mv default setting). use the worst-case maximum value for r ds(on ) from the mosfet n l data sheet, and add some margin for the rise in r ds(on) over tempera- ture. a good general rule is to allow 0.5% additional resistance for each c of the mosfet junction temper- ature rise. connect ilim to vl for the default 250mv (typ) current- limit threshold. for an adjustable threshold, connect a resistive-divider from vl to ilim to gnd. the 500mv to 2.5v external adjustment range corresponds to a 106mv to 530mv current-limit threshold. when adjust- ing the current limit, use 1% tolerance resistors and a 10a divider current to prevent a significant increase in the current-limit tolerance. v r i lir i valley low ds on load max load max () () () () > ? ? ? ? ? ? - 2 ii lir i peak load max load max =+ ? ? ? ? ? ? () () 2 bst c1 d1 c2 r2 r1 n h n l c bst r pok r comp c comp c out c in dh lx l output 1.25v to 5v* input 4.5v to 28v dl out gnd fb in vl ilim pok comp max1864 max1865 * for output voltages > 5v, see "output voltage selection." figure 4. adjustable output voltage
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 16 ______________________________________________________________________________________ mosfet selection the max1864/max1865s step-down controller drives two external logic-level n-channel mosfets as the cir- cuit switch elements. the key selection parameters are: on-resistance (r ds(on) ) maximum drain-to-source voltage (v ds(max) ) minimum threshold voltage (v th(min) ) total gate charge (q g ) reverse transfer capacitance (c rss ) the high-side n-channel mosfet must be a logic-level type with guaranteed on-resistance specifications at v gs 4.5v. select the high-side mosfet s r ds(on) so i peak x r ds(on) 225mv for the current-sense range. for maximum efficiency, choose a high-side mosfet (n h ) that has conduction losses equal to the switching losses at the optimum input voltage. check to ensure that the conduction losses at minimum input voltage don t exceed the package thermal limits or violate the overall thermal budget. check to ensure that the con- duction losses plus switching losses at the maximum input voltage don t exceed package ratings or violate the overall thermal budget. the low-side mosfet (n l ) provides the current-limit signal, so choose a mosfet with an r ds(on) large enough to provide adequate circuit protection (see setting the current-limit ): use the worst-case maximum value for r ds(on) from the mosfet n l data sheet, and add some margin for the rise in r ds(on) over temperature. a good general rule is to allow 0.5% additional resistance for each c of the mosfet junction temperature rise. ensure that the max1864/max1865 dl gate drivers can drive n l ; in other words, check that the dv/dt caused by n h turning on does not pull up the n l gate due to drain-to-gate capacitance, causing cross-conduction problems. mosfet package power dissipation often becomes a dominant design factor. i 2 r power losses are the great- est heat contributor for both high-side and low-side mosfets. i 2 r losses are distributed between n h and n l according to duty factor as shown in the equations below. generally, switching losses affect only the high- side mosfet since the low-side mosfet is a zero-volt- age switched device when used in the buck topology. gate-charge losses are dissipated by the driver and do not heat the mosfet. calculate the temperature rise according to package thermal-resistance specifications to ensure that both mosfets are within their maximum junction temperature at high ambient temperature. the worst-case dissipation for the high-side mosfet (p nh ) occurs at both extremes of input voltage, and the worst-case dissipation for the low-side mosfet (p nl ) occurs at maximum input voltage. where i gate is the dh driver peak output current capa- bility (1a typ), and 20ns is the dh driver inherent rise/fall-time. to reduce emi caused by switching noise, add a 0.1f ceramic capacitor from the high- side switch drain to the low-side switch source, or add resistors (47 ? max) in series with dl and dh to increase the switches turn-on and turn-off times (figure 5). the minimum load current should exceed the high-side mosfet s maximum leakage current over temperature if fault conditions are expected. input capacitor the input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit s switching. the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents defined by the following equation: for most applications, nontantalum capacitors (ceram- ic, aluminum, polymer, or os-con) are preferred due to their robustness with high inrush currents typical of systems with low-impedance battery inputs. additionally, two (or more) smaller value low-esr capacitors can be connected in parallel for lower cost. choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current for optimal circuit long-term reliability. ii vvv v rms load out in out in = () - duty cycle d v v pvi vc i pird pp p pi r d out in nh switching in load osc in rss gate nh conduction load ds on nh nh total nh switching nh conduction nl load ds on nl : () () () () ( ) () () = =? ? ? ? ? ? ? = =+ = () 2 2 1- r v i ds on valley valley () =
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 17 output capacitor the key selection parameters for the output capacitor are the actual capacitance value, the equivalent series resistance (esr), and voltage-rating requirements, which affect the overall stability, output ripple voltage, and transient response. the output ripple has two components: variations in the charge stored in the output capacitor, and the voltage drop across the capacitor s esr caused by the current into and out of the capacitor: the output voltage ripple as a consequence of the esr and output capacitance is: where i p-p is the peak-to-peak inductor current (see inductor selection ). these equations are suitable for initial capacitor selection, but final values should be set by testing a prototype or evaluation circuit. as a gener- al rule, a smaller ripple current results in less output rip- ple. since the inductor ripple current is a factor of the inductor value and input voltage, the output voltage rip- ple decreases with larger inductance but increases with lower input voltages. with low-cost aluminum electrolytic capacitors, the esr-induced ripple can be larger than that caused by the current into and out of the capacitor. consequently, high-quality low-esr aluminum-electrolytic, tantalum, polymer, or ceramic filter capacitors are required to minimize output ripple. best results at reasonable cost are typically achieved with an aluminum-electrolytic capacitor in the 470f range, in parallel with a 0.1f ceramic capacitor. since the max1864/max1865 use a current-mode con- trol scheme, the output capacitor forms a pole that affects circuit stability (see compensation design ). furthermore, the output capacitor s esr also forms a zero. the max1864/max1865s response to a load transient depends on the selected output capacitor. after a load transient, the output instantly changes by esr ? ? i load . before the controller can respond, the output will sag further, depending on the inductor and output capacitor values. after a short period of time (see typical operating characteristics ), the controller responds by regulating the output voltage back to its nominal state. for appli- cations that have strict transient requirements, low-esr high-capacitance electrolytic capacitors are recom- mended to minimize the transient voltage swing. do not exceed the capacitor s voltage or ripple-current ratings. compensation design the max1864/max1865 controllers use an internal transconductance error amplifier whose output com- pensates the control loop. connect a series resistor and capacitor between comp and gnd to form a pole- zero pair. the external inductor, high-side mosfet, output capacitor, compensation resistor, and compen- sation capacitor determine the loop stability. the induc- tor and output capacitor are chosen based on performance, size, and cost. additionally, the compen- sation resistor and capacitor are selected to optimize control-loop stability. the component values shown in the standard application circuits (figures 1 and 6) yield stable operation over a broad range of input-to-output voltages. the controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the max1864/max1865 use the voltage across the high- side mosfet s r ds(on) to sense the inductor current. using the current-sense amplifier s output signal and the amplified feedback voltage, the control loop deter- mines the peak inductor current by: v i esr v i c i vv l v v ripple esr p p ripple c pp out sw pp in out sw out in () () = = ? = ? ? ? ? ? ? ? ? ? ? ? ? ? - - - - 2 vv v ripple ripple esr ripple c =+ () () bst n h r gate (optional) n l r gate (optional) c bst dh lx l to vl dh gnd max1864 max1865 figure 5. reducing the switching emi
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 18 ______________________________________________________________________________________ where a vcs is the current-sense amplifier s gain (4.9 typ), a vea is the dc gain of the error amplifier (2000 typ), and v out(nominal) is the output voltage set by the feedback resistive-divider (internal or external). since the output voltage is a function of the load cur- rent and load resistance, the total dc loop gain (a v(dc) ) is approximately: the compensation capacitor (c comp ) creates the dom- inant pole. due to the current-mode control scheme, the output capacitor also creates a pole in the system that is a function of the load resistance. as the load resistance increases, the frequency of the output capacitor s pole decreases. however, the dc loop gain increases with larger load resistance, so the unity gain bandwidth remains fixed. additionally, the compensa- tion resistor and the output capacitor s esr both gener- ate zeros. therefore, to achieve stable operation, use the following procedure to properly compensate the system: 1) first, select the desired crossover frequency. the crossover frequency must be less than both 1/5th the switching frequency and 1/3rd the zero frequen- cy set by the output capacitor s esr: 2) next, determine the pole set by the output capacitor and the load resistor: 3) determine the compensation resistor required to set the desired crossover frequency: where the error amplifier s transconductance (g m ) is 100s (see electrical characteristics ). 4) finally, select the compensation capacitor: boost-supply diode a signal diode, such as the 1n4148, works well in most applications. if the input voltage goes below 6v, use a small 20ma schottky diode for slightly improved effi- ciency and dropout characteristics. do not use large power diodes, such as the 1n5817 or 1n4001, since high junction capacitance can charge up vl to exces- sive voltages. linear regulator controllers positive output voltage selection the max1864/max1865s positive linear regulator out- put voltages are set by connecting a voltage-divider from the output to fb_ to gnd (figure 6). select r4 in the 5k ? to 50k ? range. calculate r3 with the following equation: where v fb = 1.24v, and v out may range from 1.24v to 30v. negative output voltage selection (max1865) the max1865 s negative output voltage is set by con- necting a voltage-divider from the output to fb5 to a positive voltage reference (figure 6). select r6 in the 5k ? to 50k ? range. calculate r5 with the following equation: where v ref is the positive reference voltage used, and v out may be set between 0 and -20v. if the negative regulator is used, the out pin must be connected to a voltage supply between 2v and 5v that can source at least 25ma. typically, the out pin is connected to the step-down converter s output. however, if the step-down converter s output voltage is set higher than 5v, out may be connected to one of the positive linear regulators with an output voltage between 2v and 5v. rr v v out ref 56 = ? ? ? ? ? ? rr v v out fb 34 1 = ? ? ? ? ? ? ? ? ? ? ? ? ? ? - c r comp comp pole out ? 1 2 () r ga comp c m v dc pole out = ? ? 2000 () ( ) ?= = pole out out load load max out out cr i cv () () 1 22 ? ? c out esr sw cr and 1 65 vr vr ref load out nominal ds on ()() 400 a i i vr a vra vdc peak load ref load vea out nominal ds on vcs () ()() ? i vva vra peak out ref vea out nominal ds on vcs = ()()
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 19 bst c1 1 f d1 central cmpsh-3 c2 1 f n h n l c bst 0.1 f r pok 100k ? c comp c out 470 f c in 470 f dh lx t1 input 9v to 18v dl out gnd in vl ilim pok comp max1865 fb 8.2nf r comp 47k ? r nh 10 ? 1 r nl 10 ? r be2 220 ? c3 10 f q1 tip30 r1 10k ? v out2 2.5v at 500ma c4 10 f t1 r2 10k ? r be3 220 ? q2 2n3905 c6 10 f r3 30k ? r4 10k ? c7 10 f v out3 5.0v at 100ma c5 470 f d2 nihon ep05q03l b2 fb2 b3 fb3 r be4 220 ? q3 tip30 c9 10 f r5 30k ? r6 10k ? c10 10 f c8 470 f d3 nihon ep05q03l v out3 12v at 100ma b4 fb4 t1 4 d4 nihon ec10qs10 c11 470 f fb5 b5 q4 tip29 r10 470 ? connect to v out3 r7 50k ? c13 10 f r8 120k ? v out5 -12v at 50ma c15 10nf r be5 220 ? c be5 2200pf c12 10 f to logic v out1 3.3v at 1a c be2 2200pf 1 fairchild fds6912a c be3 4700pf t1 2 c be4 2200pf r9 470 ? c14 10nf r snub 300 ? c snub 100pf figure 6. standard max1865 application circuit
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 20 ______________________________________________________________________________________ transistor selection the pass transistors must meet specifications for cur- rent gain (h fe ), input capacitance, collector-emitter sat- uration voltage, and power dissipation. the transistor s current gain limits the guaranteed maximum output cur- rent to: where i drv is the minimum base-drive current, and r be (220 ? ) is the pullup resistor connected between the transistor s base and emitter. furthermore, the transis- tor s current gain increases the linear regulator s dc loop gain (see stability requirements ), so excessive gain will destabilize the output. therefore, transistors with current gain over 100 at the maximum output cur- rent, such as darlington transistors, are not recom- mended. the transistor s input capacitance and input resistance also create a second pole, which could be low enough to destabilize the output when heavily loaded. the transistor s saturation voltage at the maximum out- put current determines the minimum input-to-output voltage differential that the linear regulator will support. alternatively, the package s power dissipation could limit the useable maximum input-to-output voltage dif- ferential. the maximum power dissipation capability of the transistor s package and mounting must exceed the actual power dissipation in the device. the power dissi- pated equals the maximum load current times the maxi- mum input-to-output voltage differential: stability requirements the max1864/max1865 linear regulators use an inter- nal transconductance amplifier to drive an external pass transistor. the transconductance amplifier, pass transistor s specifications, the base-emitter resistor, and the output capacitor determine the loop stability. if the output capacitor and pass transistor are not proper- ly selected, the linear regulator will be unstable. the transconductance amplifier regulates the output voltage by controlling the pass transistor s base cur- rent. since the output voltage is a function of the load current and load resistance, the total dc loop gain (a v (ldo) ) is approximately: where v t is 26mv, and i bias is the current through the base-to-emitter resistor (r be ). this bias resistor is typical- ly 220 ? , providing approximately 3.2ma of bias current. the output capacitor creates the dominant pole. however, the pass transistor s input capacitance creates a second pole in the system. additionally, the output capacitor s esr generates a zero, which may be used to cancel the second pole if necessary. therefore, to achieve stable operation, use the following equations to verify that the linear regulator is properly compensated: 1) first, determine the dominant pole set by the linear regulator s output capacitor and the load resistor: 2) next, determine the second pole set by the base-to- emitter capacitance (including the transistor s input capacitance), the transistor s input resistance, and the base-to-emitter pullup resistor: 3) a third pole is set by the linear regulator s feedback resistance and the capacitance between fb_ and gnd, including 20pf stray capacitance: 4) if the second and third poles occur well after unity- gain crossover, the linear regulator will remain stable: however, if the esr zero occurs before unity-gain crossover, cancel the zero with pole(fb) by changing circuit components such that: ?>? pole cbe pole cldo v ldo a () ( )() 2 ?= pole fb fb crr () (|| ) 1 212 ?= () = + pole cbe be be in npn be load t fe be be t fe cr r ri vh crvh () () || 1 2 2 ?= = =? pole cldo ldo load load max ldo ldo v ldo pole cldo cr i cv unity gain crossover a () () () ( ) 1 22 a v ih i v v ldo t bias fe load ref () . ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? 55 1 pi v v i v load max ldoin out load max ce = () = () () - ii v r h load max drv be be fe min () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? -
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 21 do not use output capacitors with more than 200m ? of esr. typically, more output capacitance provides the best solution, since this also reduces the output voltage drop immediately after a load transient. linear regulator output capacitors connect at least a 1f capacitor between the linear regulator s output and ground, as close to the max1864/max1865 and external pass transistors as possible. depending on the selected pass transistor, larger capacitor values may be required for stability (see stability requirements ). furthermore, the output capacitor s esr affects stability, providing a zero that may be necessary to cancel the second pole. use out- put capacitors with an esr less than 200m ? to ensure stability and optimum transient response. once the minimum capacitor value for stability is deter- mined, verify that the linear regulator s output does not contain excessive noise. although adequate for stabili- ty, small capacitor values may provide too much band- width, making the linear regulator sensitive to noise. larger capacitor values reduce the bandwidth, thereby reducing the regulator s noise sensitivity. if noise on the ground reference causes the design to be marginally stable for the negative linear regulator, bypass the negative output back to its reference volt- age (v ref , figure 7). this technique reduces the differ- ential noise on the output. base-drive noise reduction the high-impedance base driver is susceptible to sys- tem noise, especially when the linear regulator is lightly loaded. capacitively coupled switching noise or induc- tively coupled emi onto the base drive causes fluctua- tions in the base current, which appear as noise on the linear regulator s output. keep the base-drive traces away from the step-down converter and as short as possible to minimize noise coupling. resistors in series with the gate drivers (dh and dl) reduce the lx switching noise generated by the step-down converter (figure 5). additionally, a bypass capacitor may be placed across the base-to-emitter resistor (figure 7). this bypass capacitor, in addition to the transistor s input capacitance, could bring in a second pole that will destabilize the linear regulator (see stability requirements ). therefore, the stability requirements determine the maximum base-to-emitter capacitance: where c in(q) is the transistor s input capacitance, and f pole(cbe) is the second pole required for stability. transformer selection in systems where the step-down controller s output is not the highest voltage, a transformer may be used to provide additional postregulated, high-voltage outputs. the transformer generates unregulated, high-voltage supplies that power the positive and negative linear regulators. these unregulated supply voltages must be high enough to keep the pass transistors from saturat- ing. for positive output voltages, connect the trans- former as shown in figure 6 where the minimum turns ratio (n) is determined by: where v sat is the pass transistor s saturation voltage under full load. for negative output voltages (max1865 n vvv v pos ldo pos sat diode out ++ ? ? ? ? ? ? () -1 c ri vh rvh c be pole cbe be load t fe be t fe in q ? + ? ? ? ? ? ? 1 2 () () - ? pole fb out esr cr () 1 2 c byp v neg v sup q pass c ldo r be c be r1 r2 b_ a) positive output voltage b) negative output voltage (max1865 only) fb_ max1864 max1865 v pos c byp v ref v sup q pass c neg r be c be r4 r3 bf5 b5 max1865 figure 7. base-drive noise reduction
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 22 ______________________________________________________________________________________ only), connect the transformer as shown in figure 6, where the minimum turns ratio is determined by: since power transfer occurs when the low-side mos- fet is on (dl = high), the transformer cannot support heavy loads with high duty cycles. snubber design the max1864/max1865 use a current-mode control scheme that senses the current across the high-side mosfet (n h ). immediately after the high-side mosfet has turned on, the max1864/max1865 use a 60ns cur- rent-sense blanking period to minimize noise sensitivity. when the mosfet turns on, however, the transformer s secondary inductance and the diode s parasitic capac- itance form a resonant circuit that causes ringing. reflected back through the transformer to the primary side, these oscillations across the high-side mosfet may last longer than the blanking period. a series rc snubber circuit at the diode (figure 6) increases the damping factor, allowing the ringing to settle quickly. applications with multiple transformer windings require only one snubber circuit on the highest output voltage. applications with low turn ratios (1:1), such as the max1864 typical application circuit (figure 1), may not require a snubber curcuit. the diode s parasitic capacitance can be estimated using the diode s reverse voltage rating (v rrm ), current capability (i o ), and recovery time (t rr ). a rough approximation is: for the ec10qs10 nihon diode used in figure 6, the capacitance is roughly 15pf. the output snubber must only dampen the ringing, so the initial turn-on spike that occurs during the blanking period remains preset. a 100pf capacitor works well in most applications; larger capacitance values require more charge, thereby increasing the power dissipation. the snubber s time constant (t snub ) must be smaller than the 100ns blanking time. a typical rc time con- stant of approximately 30ns was chosen for figure 6: minimum load requirements (linear regulators) under no-load conditions, leakage currents from the pass transistors supply the output capacitor, even when the transistor is off. generally, this is not a prob- lem since the feedback resistors current drains the excess charge. however, charge may build up on the output capacitor over temperature, making v ldo rise above its set point. care must be taken to ensure that the feedback resistors current exceeds the pass tran- sistor s leakage current over the entire temperature range. applications information pc board layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. follow these guidelines for good pc board layout: 1) place the power components first, with ground ter- minals adjacent (n l source, c in , c out ). if possible, make all these connections on the top layer with wide, copper-filled areas. keep these high-current paths short, especially at ground terminals. 2) mount the max1864/max1865 adjacent to the switching mosfets to keep in-lx current-sense lines, lx-gnd current-limit sense lines, and the dri- ver lines (dl and dh) short and wide. the current- sense amplifier inputs are connected between in and lx, so these pins must be connected as close as possible to the high-side mosfet. the current- limit comparator inputs are connected between lx and gnd, but accuracy is not as important, so give priority to the high-side mosfet connections. the in, lx, and gnd connections to the mosfets must be made using kelvin sense connections to guaran- tee current-sense and current-limit accuracy. 3) group the gate-drive components (bst diode and capacitor, in bypass capacitor) together near the max1864/max1865. 4) all analog grounding must be done to a separate solid copper ground plane, which connects to the max1864/max1865 at the gnd pin. this includes the vl bypass capacitor, feedback resistors, com- pensation components (r comp , c comp ), and adjustable current-limit threshold resistors connect- ed to ilim. r t c ns c snub snub snub snub == 30 c it v diode orr rrm = n vvv v neg ldo neg sat diode out ++ ? ? ? ? ? ? ? ? || ()
5) ensure all feedback connections are short and direct. place the feedback resistors as close to the max1864/max1865 as possible. 6) when trade-offs in trace lengths must be made, it s preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and low-side mosfet or between the inductor and output filter capacitor. 7) route high-speed switching nodes away from sensi- tive analog areas (b_, fb_, comp, ilim). regulating high voltage the linear regulator controllers can be configured to regulate high output voltages by adding a cascode transistor to buffer the base-drive output. for example, to generate an output voltage between 30v and 60v, add a 2n5550 high-voltage npn transistor as shown in figure 8a where v bias is a dc voltage between 3v and 20v that can source at least 1ma. r drop protects the cascode transistor by decreasing the voltage across the transistor when the pass transistor saturates. similarly, to regulate a negative output voltage between -20v and -120v, add a 2n5401 high-voltage pnp tran- sistor as shown in figure 8b. chip information transistor count: 1617 process: bicmos max1864/max1865 xdsl/cable modem triple/quintuple output power supplies ______________________________________________________________________________________ 23 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 in vl bst dh fb out comp pok lx dl gnd ilim fb3 b3 fb2 b2 12 11 9 10 fb5 b5 fb4 b4 max1865 20 qsop top view pin configurations (continued)
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies 24 ______________________________________________________________________________________ supplier phone fax internet inductors and transformers coilcraft 847-639-6400 847-639-1469 http://www.coilcraft.com coiltronics 561-241-7876 561-241-9339 http://www.coiltronics.com sumida usa 847-956-0666 847-956-0702 http://www.sumida.com toko 847-297-0070 847-699-1194 http://www.toko.co.jp capacitors avx 803-946-0690 803-626-3123 http://www.avxcorp.com kemet 408-986-0424 408-986-1442 http://www.kemet.com panasonic 847-468-5624 847-468-5815 http://www.panasonic.com sanyo 619-661-6835 619-661-1055 http://www.sanyo.com taiyo yuden 408-573-4150 408-573-4159 http://www.t-yuden.com diodes central semiconductor 516-435-1110 516-435-1824 http://www.centralsemi.com international 310-322-3331 310-322-3332 http://www.irf.com nihon 847-843-7500 847-843-2798 http://www.niec.co.jp on semiconductor 602-303-5454 602-994-6430 http://www.onsemi.com zetex 516-543-7100 516-864-7630 http://www.zetex.com table 1. component suppliers c byp v neg v sup q pass q cascode q cascode c pos r be r drop c drop r drop c drop r1 r2 b_ a) positive output voltage with cascoded base drive b) negative output voltage (max1865 only) with cascoded base drive fb_ max1864 max1865 v bias v pos c byp v ref v sup q pass c neg r be r4 r3 fb5 b5 max1865 figure 8. high-voltage linear regulation
max1864/max1865 xdsl/cable modem triple/quintuple output power supplies maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information qsop.eps

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